The present invention relates in general to the field of semiconductor product testing, and more particularly to a wafer interposer for testing and assembly into a conventional package.
The three stages of semiconductor device manufacture are wafer fabrication, assembly and testing. The testing stage always includes an evaluation of the electrical connections within the device, and often includes burn-in testing as well. In a conventional manufacturing process, before testing is done, the semiconductor wafer is diced into individual semiconductor dies, and the dies are assembled into packages. The purpose of the package is to protect the semiconductor die as well as provide connections that allow the package to be attached to a testing apparatus or printed circuit board. The fact that the testing of the individual dies does not take place until the dies have been packaged, increases the cost. This increased cost stems from the greater complexity, size, and quantity of the testing apparatus, as well as the difficulty of manipulating large quantities of separately packaged dies.
In addition to the tooling and labor costs associated with electrical and burn-in testing of individually packaged dies, there is also the wasted expense of packaging the dies that will subsequently be found to be defective. Since in a conventional process all dies must be packaged before any testing can be done, this means that all defective die will necessarily be packaged, and the expense of doing so is complete waste. For example, if 6%, a conservative estimate, of the dies fail either the electrical or burn-in testing, that is 60 die packaging operations that are wasted for every 1000 dies that are produced. The ability to test the dies before the packaging operations would obviously reduce production costs.
The savings associated with a wafer level testing protocol are multifold. In addition to the savings associated with the elimination of unnecessary packaging operations, inventory carrying costs are reduced because the processing cycle times are reduced since xe2x80x9cgoodxe2x80x9d dies are identified earlier in the manufacturing process.
Accordingly, there is a need for a wafer interposer and a method that allows for the testing of semiconductor dies while still assembled in wafer form. It is also important that the wafer interposer and method does not impede the ability to package the dies after they have passed the testing and have been cut from the wafer.
The present invention provides a wafer testing interposer and semiconductor wafer assembly that allows testing at the wafer level before dicing or singulating. It also allows the direct packaging of the singulated chip assemblies. As a result, the number of manufacturing operations is reduced, which in turn increases first pass yields. In addition, manufacturing time is decreased, thereby improving cycle times and avoiding additional costs.
More specifically, the present invention provides a number of apparatus and methods for interfacing semiconductor wafers containing a multitude of semiconductor dies, with testing equipment. The interposer, and its use when attached to a semiconductor wafer, will greatly improve the processing of semiconductor dies. It will eliminate the need to singulate, package and test each die individually. The savings in time and packaging expense alone will be substantial, but the removal of the defective die at an earlier stage than is currently possible will also add greatly to the economic advantages produced by the present invention.
The present invention provides a wafer testing interposer. The interposer is comprises a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch that the first electrical terminals, and they are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathways.
The present invention also provides a method for producing a wafer testing interposer including the steps of providing a support having an upper surface and a lower surface. Attaching one or more solder bumps to the lower surface of the support. Attaching one or more first electrical terminals to the upper surface. The attachment of the first electrical terminals substantially corresponds to the position of the solder bumps, and forming a pattern. Creating one or more first electrical pathways passing through the support and connecting the solder bumps to the first electrical terminals. Attaching one or more second electrical terminals to the upper surface within the pattern formed by the first electrical terminals. Attaching one or more second electrical pathways connecting the first electrical terminals to the second electrical terminals.
In addition, the present invention also provides a wafer testing interposer and semiconductor wafer assembly comprising a wafer testing interposer that comprises a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch that the first electrical terminals, and they are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathways. A semiconductor wafer includes one or more semiconductor dies and having a first and a second surface. One or more third electrical terminals on the first surface of the semiconductor wafer and substantially aligned with the outer edges of the semiconductor dies. The wafer testing interposer aligned with the semiconductor wafer so that the third electrical terminals on the first surface of the semiconductor wafer correspond with the solder bumps on the lower surface of the wafer testing interposer.
Moreover, the present invention also provides a method for producing a wafer testing interposer and semiconductor wafer assembly comprising the steps of creating a wafer testing interposer including the steps of providing a support having an upper surface and a lower surface. Attaching one or more solder bumps to the lower surface of the support. Attaching one or more first electrical terminals to the upper surface. The attachment of the first electrical terminals substantially corresponds to the position of the solder bumps, and forming a pattern. Creating one or more first electrical pathways passing through the support and connecting the solder bumps to the first electrical terminals. Attaching one or more second electrical terminals to the upper surface within the pattern formed by the first electrical terminals. Attaching one or more second electrical pathways connecting the first electrical terminals to the second electrical terminals. Creating a semiconductor wafer including one or more semiconductor dies, and having a first and a second surface. Creating on at least one of the semiconductor dies, one or more third electrical terminals that are substantially aligned with the outer edges of the semiconductor dies. Aligning the wafer testing interposer with the semiconductor wafer so that the solder bumps on the lower surface of the wafer testing interposer correspond with the third electrical terminals on the first surface of the semiconductor wafer.